1. Field of the Invention
The present invention relates to semiconductor integrated circuits and, in particular, to techniques for obtaining an ECL characteristic output using CMOS transistor elements.
2. Discussion of the Prior Art
High speed integrated circuits are often designed in emitter-coupled-logic (ECL) technology which is well known for its high speed operation. ECL is a non-saturating form of digital logic that eliminates transistor storage time as a speed-limiting characteristic. However, as a trade-off for high speed operation, ECL is the least efficient integrated circuit technology in terms of power dissipation, making it unsuitable for many high density VLSI circuit applications.
Complementary metal oxide semiconductor (CMOS) technology, on the other hand, provides high density circuitry for VLSI applications with low power dissipation.
Therefore, a combination of CMOS VLSI circuits with ECL-compatible input/output buffers provides fast, high-density circuits that have relatively low power dissipation.
Schumacher et al, "CMOS Subnanosecond True-ECL Output Buffer", IEEE Journal of Solid-Sate Circuits, Vol. 25, No. 1, February 1990, pp. 150-154, describe an ECL-compatible output buffer fabricated utilizing CMOS technology.
The Schumacher et al circuit, shown in FIG. 1, requires that the operational amplifier 10 utilized to drive the P-channel output transistor 12 switch from the ECL high level reference voltage VOH to the ECL low level reference voltage VOL on the fly as the output buffer switches. This limits the logic transition time and complicates the criteria for stable op amp operation. The Schumacher et al approach also necessitates the duplication of the op amp circuit for every output buffer.